Application Note Networking Silicon 317506-001 Revision 2.9 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 82540EP/82541(PI/GI/EI) Gigabit Ethernet Controllers and the 82562EZ/82562EX Platform LAN Connect components may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries. Copyright © 2008, Intel Corporation. *Third-party brands and names are the property of their respective owners. ii 82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide Revision History Revision 0.25 0.75 1.0 1.5 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 Revision Date Aug 2002 Sep 2002 Oct 2002 Sep 2003 Mar 2004 July 2004 Oct 2004 Nov 2004 Jan 2005 Jan 2005 Apr 2005 June 2006 June 2006 January 2008 Description Initial publication of preliminary design guide information. Revised Design Guide information. Replaced reference design schematic. Revised EEPROM map and bit descriptions. Revised Design Guide Information Removed EEPROM information due to publication of separate guides. Published revised design guide information: • Added 82541GI coverage • Removed Confidential status • Updated schematics, removing redundant caps • Revised LAN disable circuit Published revised and updated design guide information: • Added information for the 82541PI • Updated schematics to include 82541PI Revised title for more clarification. Added crystal start-up information. Information includes: • New crystal parameters • Crystal selection guidelines • Crystal validation methods • Crystal testing methods Added 82562EX applicability. Added new values for TX and RX terminations (next to LAN silicon). New values are now 110 Ω for both TX and RX terminations. Added new starting values for RBIAS100 and RBIAS10. New starting values are now 649 Ω for RBIAS100 and 619 Ω for RBIAS10. Updated reference schematics Read the full 82540EP/82541(PI/GI/EI) & 82562EZ(EX) Dual Footprint Design Guide.