주요 정보

제품 콜렉션
MAX® V CPLD
상태
Launched
출시일
2010
리소그래피
180 nm

리소스

로직 요소(LE)
80
Equivalent Macrocells
64
Pin-to-pin Delay
7.5 ns
User Flash Memory
8 Kb
Logic Convertible To Memory

기능

Internal Oscillator
Fast Power-on Reset
Boundary-scan JTAG
JTAG ISP
Fast Input Registers
Programmable Register Power-up
JTAG Translator
Real-time ISP
MultiVolt I/Os†
1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V
I/O Power Banks
2
Maximum Output Enables
54
LVTTL/LVCMOS
Emulated LVDS Outputs
Schmitt Triggers
Programmable Slew Rate
Programmable Pull-up Resistors
Programmable GND Pins
Open-drain Outputs
Bus Hold

패키지 사양

패키지 옵션
M64, M68, E64, T100
패키지 크기
4.5mm, x 4.5mm, 5mm x 5mm, 9mm x 9mm, 16mm x 16mm

보조 정보

추가 정보 URL