Intel® Quartus® Prime Software Suite

The Intuitive High-Performance Design Environment.

Overview

The revolutionary Intel® Quartus® Prime Design Software includes everything you need to design for Intel® FPGAs, SoCs, and complex programmable logic device (CPLD) from design entry and synthesis to optimization, verification, and simulation. Dramatically increased capabilities on devices with multi-million logic elements are providing designers with the ideal platform to meet next-generation design opportunities.

More details are available in the Quick-Start for Intel® Quartus® Prime Pro Edition Software and the Getting Started User Guide: Intel® Quartus® Prime Pro Edition.

Features and Downloads

To compare different Intel® Quartus® Prime Editions, please visit the getting started page.

What’s New in 21.1

Intel® Quartus® Prime Pro Edition Software v21.1 supports the newest FPGA family:

Intel® Agilex™ FPGAs

The Intel® Agilex™ FPGA family leverages heterogeneous 3D system-in-package (SiP) technology to integrate Intel’s first FPGA fabric built on 10 nm SuperFin Technology and 2nd Generation Intel® Hyperflex™ FPGA Architecture to deliver up to 45% higher performance (geomean vs. Intel® Stratix® 10)1 or up to 40% lower power1 for applications in Data Center, Networking, and Edge compute. Intel® Agilex™ SoC FPGAs also integrate the quad-core Arm Cortex-A53 processor to provide high system integration.

The Intel® Quartus® Prime Pro Edition Software v21.1 is an intuitive design environment that will help you meet your power and performance requirements and reduce your overall development effort. Features in the v21.1 release include:

  • Improvements for Intel® Agilex™ FPGA power, performance, runtime, memory, and logic utilization
  • New and improved Design Assistant design rules for synthesis, clock domain crossing (CDC), reset domain crossing (RDC), and timing
  • Hierarchical grouping of design rule checking (DRC)
  • Rule-tagging and filtering
  • DRC waiver mechanism
  • New ease-of-use reports for static timing analysis, design closure, synthesis, and undefined entities
  • More cross-probing and runtime improvements for reports
  • Locate SDC constraints in a file
  • Faster ECO compiles for post-fit tap targets in Signal Tap II Logic Analyzer
  • Flow-Resume feature
  • Improved GUI display for higher resolution monitors
  • Remote debug over Ethernet and PCI Express using Nios® II processor
  • Mark signals for debug (Beta) feature for register transfer level (RTL) development
  • Questa*-Intel® FPGA Edition Software (Beta Evaluation)
  • Updates to IP including
  • PCI Express
  • Interlaken
  • JESD
  • Transceivers
  • CPRI
  • ORAN
  • Ethernet

Free Hands-On Training

Register for FREE instructor-led classes for hands-on training to enhance your FPGA design skills.

  • The Intel® Quartus® Prime Software: Foundation
  • Using Intel® Stratix® 10 and Intel® Agilex™ SoC FPGAs
  • Introduction to the Platform Designer System Integration Tool
  • The Quartus Software Debug Tools
  • Timing Closure with Intel® Quartus® Prime Pro Software
  • Intel® Quartus® Prime Pro Software Timing Analysis
  • Using Intel® SoC FPGAs
  • Introduction to Verilog HDL
  • Advanced Verilog HDL Design Techniques
  • And more!

Documentation and Support

Find technical documentation, videos, and training courses for Intel® Quartus® Prime Design Software.

Subscribe to the Intel® FPGA Newsletter

Do you want the latest info about Intel® FPGAs, Programmable Accelerators, and power solutions? Looking for hot tips on training and tools? Click here to subscribe to the Intel Inside Edge Monthly Newsletter.

이 양식을 제출하면 귀하가 18세 이상의 성인이며 인텔의 비즈니스 용도를 위해 귀하의 개인정보를 인텔에 공유하는 데 동의한 것으로 간주됩니다. 인텔의 웹 사이트 및 커뮤니케이션에는 당사의 개인정보 취급방침 이용 약관이 적용됩니다.
이 양식을 제출하면 귀하가 18세 이상의 성인이며 인텔의 비즈니스 용도를 위해 귀하의 개인정보를 인텔에 공유하는 데 동의한 것으로 간주됩니다. 이메일과 전화로 제공되는 최신 인텔 기술 및 업계 동향 소식을 구독하는 데도 동의하게 됩니다. 언제든지 구독 취소할 수 있습니다. 인텔의 웹 사이트 및 커뮤니케이션에는 당사의 개인정보 취급방침 이용 약관이 적용됩니다.

제품 및 성능 정보

1

성능은 사용, 구성 및 기타 요인에 따라 다릅니다. www.Intel.co.kr/PerformanceIndex 에서 자세한 정보를 확인하십시오.

성능 결과는 구성에 표시된 날짜에 진행된 테스트를 기반으로 하며 공개된 모든 업데이트가 반영되어 있지 않을 수도 있습니다. 구성 백업 상세 정보를 확인하십시오. 어떤 제품 또는 구성 요소도 절대적으로 안전할 수는 없습니다.

비용과 결과는 다를 수 있습니다.