What's New in Intel® Quartus® Prime Software

Power and Performance

Intel® Agilex™ Device Support

The v20.3 release of the Intel® Quartus® Prime Pro Edition Software provides support for the Intel® Agilex™ device family of FPGAs. These innovative FPGAs leverage heterogeneous 3D system-in-package (SiP) technology to integrate Intel’s first FPGA fabric built on 10nm process technology and 2nd Gen Intel® Hyperflex™ FPGA Architecture to deliver up to 40% higher performance or up to 40% lower power.1

Compilation Strategies

The compiler in Intel® Quartus® Prime Pro Edition Software is a fast, multi-faceted tool, allowing different compilation strategies that meet the designer’s needs. In addition to standard compilation, which can give you a baseline for performance, there are other compilation options available:

  • Fast compile for small designs, introduced in 20.3, can be used to get quick compiles at the beginning of the development process when only a small portion of the design has been implemented.
  • High Effort compilation is used to make the compiler maximize its effort in order to get the best performance results out a of a design.
  • Fast Preservation compilations can be used with partitioned designs. Using a previously satisfactory compilation, Fast preservation simplifies the logic of a preserved partition to only the interface between the partition boundary and the rest of the design. The use of Fast Preservation reduces the compile time required for the preserved partition and thus the overall compile time.
  • Back Annotation is used in conjunction with seed sweeping to take the best compilation from run of different seeds and use that as the starting point for additional seed sweeping after fixing in place the results of pin-placement, clocks, RAMS, DSPs or a combination of these. The results are typically higher Fmax with less variation in results. Additionally, in 20.3, a GUI for Back Annotation has been provided to make it even easier to use.
  • ECO compilation is used when only minor changes are needed to an otherwise good compile. This flow was introduced in 19.3 and has been enhanced in each release. ECO compiles can provide a compilation speedup of 5x – 10x.2 It is also replacing the Rapid Recompile flow for post-fit SignalTap changes with significant compilation speedup. For 20.3 the ability to place flipflops has been added to allow for a richer set of ECO options when doing development and debug.

Additionally, there are many other parameters available to customize your compilation strategies to meet your specific requirements.

Power and Thermal Calculator

The Power and Thermal Calculator (PTC) supports Intel® Agilex™ and Stratix® 10 FPGA devices. For these devices it replaces the older Early Power Estimator. It can be used inside the Intel® Quartus® Prime Pro Edition Software or as a standalone tool. In 20.3 the look and feel of the PTC has been improved allowing greater customization of the layout as well as tooltips to describe various parameters in the PTC. In 20.3 the Thermals tab has been introduced for Agilex™ devices, allowing the designer to do thermal analysis for the design and providing a method to obtain cooling solutions under various conditions.

Ease of Use

Design Assistant / Snapshot Viewer

The Design Assistant and Snapshot Viewer are productivity tools meant for novice and advanced users. These tools enable faster design closure by reducing the number of design iterations required and speeds every iteration with targeted sanity checks and guidance at every stage of the compilation process. Learn more about Design Assistant and Snapshot Viewer with the provided video.

In Intel® Quartus® Prime Pro Edition Software 20.3 over 30 new rules have been added to Design Assistant covering memory instantiation, clock domain crossing, and reset domain crossing. Many of the Design Assistant rules support cross probing to timing reports to make it easier to investigate paths. Additionally, a new rule classification for “fatal rule violation” has been added that will stop the compilation if that rule is found to be violated. None of the DA rules are classified as “fatal”, but any of the rules can be changed to fatal classification by the designer.

Platform Designer

Platform designer has been enhanced to improve GUI performance in Intel® Quartus® Prime Pro Edition Software 20.3. New features have been added to allow for parameter support for HDL and Blackbox IP instantiations as well as the ability to pass parameters via RTL. The Avalon Multi-Master Pipeline Bridge now supports passing the writeresponsevalid signal back to the master component. Additionally, the Avalon ST credit flow control, which provides higher performance through source flow control has been updated.

New Reports

Intel® Quartus® Prime Pro Edition Software continues to expand the rich set of compilation reports available. In the 20.3 release, several reports have been added or updated, including:

  • Report timing extra info
  • More information in Clock Transfers report
  • Route net of interest
  • Register spread
  • Hierarchical retiming restrictions
  • Pipelining information

This expanding portfolio of reports enables users to gather detailed information about routing, congestion, timing, tension, span, routing effort, and many other metrics that will provide rapid feedback for closing timing quickly.

Documentation and Support

Find technical documentation, videos, and training courses for Intel® Quartus® 
Prime Design Software.

제품 및 성능 정보

1

이 내용은 시뮬레이션 결과에 따른 인텔® Agilex™ FPGA 및 SoC 제품군과 인텔® Stratix® 10 FPGA의 비교를 기준으로 하며 변경될 수 있습니다. 본 문서에는 개발 중인 제품, 서비스 및/또는 프로세스에 대한 정보가 수록되어 있습니다. 이 문서에 제공된 모든 정보는 예고 없이 변경될 수 있습니다. 최신 예측 정보, 일정, 사양 및 로드맵을 원하시면 인텔 담당자에게 문의하십시오.
인텔® 기술의 특징과 이점은 시스템 구성에 따라 다르며 지원되는 하드웨어, 소프트웨어 또는 서비스 활성화가 필요할 수 있습니다. Intel.co.kr, OEM 또는 대리점에서 자세한 정보를 확인하세요. 어떠한 컴퓨터 시스템도 절대적으로 안전하지는 않습니다. 성능은 사용, 구성 및 기타 요인에 따라 다릅니다. www.Intel.co.kr/PerformanceIndex에서 자세한 정보를 확인하십시오.

2

벤치마크는 인텔® Stratix® 10 1S280 장치 및 Linux 64 운영 체제에서 28개의 설계에 대해 수행되었습니다. 비교는 Netlist 변경 후 기준 컴파일 시간과 ECO 컴파일 시간 사이에 수행되었습니다(ECO 변경에 이용 가능한 항목에 따라 8 - 2000). 특정 시스템의 특정 테스트에서 구성 요소의 문서 성능을 테스트하십시오. 하드웨어, 소프트웨어 또는 구성의 차이가 실제 성능에 영향을 줄 수 있습니다. 구매를 고려하고 있는 경우 다른 정보 소스도 참조하여 성능을 평가하십시오. 성능 및 벤치마크 결과에 대한 일반 정보는 http://www.intel.co.kr/benchmarks를 참조하십시오.