Qsys: The clock period of an Altera Avalon Clock Source BFM generated by Qsys is not accurate

The clock period of an Altera Avalon Clock Source bus functional model (BFM) generated by Qsys is not accurate. If you set up your design with the default clock source and then generate the testbench Qsys system and testbench simulation model, the generated testbench Qsys system uses the Altera Avalon Clock Source BFM (altera_avalon_clock_source) as the clock’s source.

To correct the clock period:

1. Open the generated altera_avalon_clock_source.sv file in <Qsys output directory>/simulation/submodules.
2. Change ‘timescale 1ns/1ns to ‘timescale 1ns/1ps. If you require a smaller time unit, use ‘timescale 1ns/1fs.
3. Change localparam CLOCK_PERIOD = 1000/CLOCK_RATE; to localparam CLOCK_PERIOD = 1000.000000/CLOCK_RATE;.