Quartus Prime® 소프트웨어 버전 16.1.2 이하의 문제로 인해 Arria® 10 SerialLite™ III 코어는 아래 표시된 유형의 "pld_10g_tx_pempty_reg 노드"와 "altera 표준 싱크로나이저stdsync_txpempty|din_s1" 사이의 경로에서 설정 타이밍 위반을 나타낼 수 있습니다.
노드에서: seriallite_iii_streaming: seriallite_iii_streaming_inst|seriallite_iii_streaming_seriallite_iii_a10_161_jvvqjaa:seriallite_iii_streaming|interlaken_native_wrapper_duplex_seriallite_iii_streaming_seriallite_iii_a10_161_zgsou7q:A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex|seriallite_iii_streaming_seriallite_iii_a10_161_zgsou7q:DUPLEX_WRAPPER.interlaken_inst|seriallite_iii_streaming_altera_xcvr_native_a10_161_koe2tsa: native_ilk_wrapper|twentynm_xcvr_native:g_xcvr_native_insts[5].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm5es:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm5es:inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg
노드까지: seriallite_iii_streaming: seriallite_iii_streaming_inst|seriallite_iii_streaming_seriallite_iii_a10_161_jvvqjaa:seriallite_iii_streaming|interlaken_native_wrapper_duplex_seriallite_iii_streaming_seriallite_iii_a10_161_zgsou7q:A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex|altera_std_synchronizer_nocut:pcs_lanes[5].stdsync_txpempty|din_s1
발사 클럭 : seriallite_iii_streaming_inst|seriallite_iii_streaming|g_xcvr_native_insts[*]|tx_pma_clk
래치 클럭 : seriallite_iii_streaming_inst| seriallite_iii_streaming|g_xcvr_native_insts[0]|tx_pma_clk
이 문제를 해결하려면 사용자가 생성된 IP .sdc 파일(seriallite_iii_streaming*.sdc)을 수정해야 합니다.
원래 . sdc contraints는 다음과 같습니다.
set_max_skew -from [get_keepers {*$module_name*|*interlaken_native_wrapper_duplex|*|twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_pcs|inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg}] -to [get_keepers {*$module_name*|interlaken_native_wrapper_duplex|stdsync_txpempty|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.85
set_net_delay -from [get_keepers {*$module_name*|*interlaken_native_wrapper_duplex|*|twentynm_xcvr_native:g_xcvr_native_insts[*].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm4:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm4:inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg}] -to [get_keepers {*$module_name*|interlaken_native_wrapper_duplex_*: A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex|altera_std_synchronizer_nocut:pcs_lanes[*].stdsync_txpempty|din_s1}] -max -get_value_from_clock_period dst_clock_period -value_multiplier 0.85
set_max_delay -from [get_keepers {*$module_name*|*interlaken_native_wrapper_duplex|*|twentynm_xcvr_native:g_xcvr_native_insts[*].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm4:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm4:inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg}] -to [get_keepers {*$module_name*|interlaken_native_wrapper_duplex_*: A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex|altera_std_synchronizer_nocut:pcs_lanes[*].stdsync_txpempty|din_s1}] 100
set_min_delay -from [get_keepers {*$module_name*|*interlaken_native_wrapper_duplex|*|twentynm_xcvr_native:g_xcvr_native_insts[*].twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm4:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm4:inst_twentynm_pcs|gen_twentynm_hssi_10g_tx_pcs.inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg}] -to [get_keepers {*$module_name*|interlaken_native_wrapper_duplex_*: A10_ILK_PHY_DPLX.interlaken_native_wrapper_duplex|altera_std_synchronizer_nocut:pcs_lanes[*].stdsync_txpempty|din_s1}] -100
다음 제한 사항으로 대체해야합니다.
설정 inst_xcvr_list [get_entity_instances twentynm_xcvr_native]
foreach each_xcvr_inst \$inst_xcvr_list {
if { [string equal "quartus_sta" \$::TimeQuestInfo(nameofexecutable)] } {
set_max_skew -from [get_keepers \$each_xcvr_inst*|*inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg] -to [get_keepers {*stdsync_txpempty|din_s1}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.85
}
set_net_delay -from [get_keepers \$each_xcvr_inst*|*inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg] -to [get_keepers {*stdsync_txpempty|din_s1}] -max -get_value_from_clock_period dst_clock_period -value_multiplier 0.85
set_max_delay -from [get_keepers \$each_xcvr_inst*|*inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg] -to [get_keepers {*stdsync_txpempty|din_s1}] 100
set_min_delay -from [get_keepers \$each_xcvr_inst*|*inst_twentynm_hssi_10g_tx_pcs~pld_10g_tx_pempty_reg.reg] -to [get_keepers {*stdsync_txpempty|din_s1}] -100
}
이 문제는 Quartus Prime® 소프트웨어의 소프트웨어 버전 17.0부터 해결되었습니다.