중요 문제
Stratix V 장치용 설계를 컴파일할 때 시스템 다음과 유사한 수많은 PLL 관련 경고 메시지가 표시될 수 있습니다. 다음:
Warning: PLL(s) placed in location FRACTIONALPLL_X0_Y1_N0
do not have a PLL clock to compensate specified - the Fitter will
attempt to compensate all PLL
Warning: PLL(s) placed in location FRACTIONALPLL_X0_Y1_N0
use multiple different clock network types - the PLL will compensate
for output clocks
Warning: PLL cross checking found inconsistent PLL clock
settings:
Warning: Node: mem_if|controller_phy_inst|memphy_top_inst|pll1~FRACTIONAL_PLL|mcntout was
found missing 1 generated clock that corresponds to a base clock with
a period of: 8.000
Warning: Clock: mem_if|ddr3_pll_write_clk was found on
node: mem_if|controller_phy_inst|memphy_top_inst|pll3|outclk with
settings that do not match the following PLL specifications:
Warning: -multiply_by (expected: 21, found: 4264000)
Warning: -divide_by (expected: 5, found: 1000000)
Warning: -phase (expected: 0.00, found: 90.00)
이러한 경고 메시지는 예상되며 무시될 수 있습니다.
이 문제에 대한 해결 방법은 없습니다. 안전하게 무시할 수 있습니다. 오류 메시지가 표시됩니다.